The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a test mode circuit.
In general, a semiconductor memory device supports a test mode so that various situations and configurations can be critically evaluated for the purpose of failure analysis. Conventionally, in order to prevent an unexpected test mode entry, a change in an address is controlled to enter into a test mode only when a test mode register set code is continuously inputted three times.
That is, as shown in FIG. 1, if a test mode command CMD is generated, for example, in synchronization with a rising edge of a clock CLK, then the address signals A<8>, A<9>, A<10> for test enable control are continuously inputted together with a test mode register set signal TMRS generated from a mode register set in synchronization with a rising edge of a clock CLK. If the test mode register set signal TMRS and the address signals A<8>, A<9>, A<10> are continuously inputted three times, a test mode enable signal TM_EN is generated, thereby performing a test mode entry.
When the next test mode is continuously performed, the test mode enable signal TM_EN is generated only when the test mode register set signal TMRS and the address signals A<8>, A<9>, A<10> are continuously inputted three times.
However, it is relatively rare that a test mode entry fails to operate when tested with a conventional general product test equipment. If a normal testing operation can be performed in a mounting configuration, then conventional techniques of testing modes may be become unnecessary. In particular, when a conventional test mode entry control methods are used, it is often inconvenient or cumbersome to insert a test command procedure, because it is likely to require considerable time to set up the conventional continuous testing configuration. That is, entering into a test mode using in a continuous test mode operation, may make the prior known conventional test mode entry control methodologies obsolete and thereby unnecessary.